A Verification-Guided Multi-Agent Framework for Reliable RTL Generation and Optimization
DOI:
https://doi.org/10.62051/r6y8jj34Keywords:
Register-transfer level; Large language models; Multi-agent systems; Automated program repair; Fault localization; Functional verification; Equivalence checking; Logic synthesis.Abstract
Large language models (LLMs) already emit syntactically plausible Verilog, yet a large share of generated designs fails functional verification, and the designs that do pass are not necessarily good implementations. We present VGMA, a verification-guided multi-agent framework that closes the loop between an RTL generator and open-source EDA tooling. VGMA synthesises a differential testbench directly from the reference port interface, compresses every failing simulation into a counterexample signature of nine semantic tags, maps that signature to a prior over repair operators, ranks suspicious lines with a backward cone-of-influence slice refined by the differing bit mask and by elaboration diagnostics, and admits a patch only after a bounded sequential equivalence proof. Every number reported here is produced by Icarus Verilog and Yosys. On 261 injected defects across 152 VerilogEval v2 problems, the full signal set places the faulty line first for 47.9% of defects (75.1% within the top five) against 31.4% (64.0%) without elaboration diagnostics, and repairs 73.3% of defects within 25 verification queries against 36.7% for an undirected search over an identical edit space, while using 40% fewer queries. On 220 real GPT-3.5-turbo and GPT-4 generations shipped with RTLLM, of which 125 fail, guided repair makes 40.0% of the 35 non-elaborating designs elaborate against 5.7% for undirected search, but end-to-end functional repair reaches only 5.6% against 1.6%: mutation corpora substantially overstate what line-local repair achieves on real LLM defects. Finally, 25.3% of functionally passing LLM designs synthesise larger than the human reference (mean 1.27x cells, worst case 18.8x), whereas a portfolio of synthesis scripts recovers only 2.0% on average, which places the optimisation opportunity at the RTL level rather than in the synthesis flow.
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